Static timing analysis (STA) is utilized to verify integrated circuit design and analyze circuit performance. In circuit design, one signal may need to arrive at a particular point in a circuit path before another signal. A timing test with respect to a pair of timing test points is typically to compare two signals at the timing test point to determine whether a particular requirement on their relative arrival time is met. The difference of the relative arrival time of two signals at the timing test point is referred to as “slack”. Two paths on which signals propagate to arrive at the pair of timing test points (e.g., clock and data pins of a flip-flop circuit) are often referred to as racing paths. Timing of integrated circuits may vary due to the effects of environmental and process variation. Typically, each source of variation to be analyzed is modeled as a parameter having an impact on a delay of a circuit path and/or a circuit. A set of parameter settings is often called a “corner.” In one example, a parameter may be set to one of its extreme values (e.g., a 3SIGMA extreme value). In such an example, one corner provides a fastest signal propagation checked in a timing analysis and the other corner provides a slowest signal propagation in a timing analysis.
Multi-corner static timing analysis is utilized to verify integrated circuit designs across multiple process corners. Such a static timing analysis may start with a set of specific parameter values, called a starting corner. In such an analysis with n parameters, there may be 2n extreme corners. As the number of parameters to test increases and the complexity of integrated circuit designs continues to grow, the analysis of the large number of extreme corners for each path of an integrated circuit becomes difficult, if not impossible, to perform in a reasonable amount of time. Reduction of the number of paths to analyze can reduce this time required to perform multi-corner timing analysis on remaining paths.